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32-channel, 3 v/5 v, single-supply, 14-bit, voltage output dac ad5382 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features guaranteed monotonic inl error: 4 lsb max on-chip 1.25 v/2.5 v, 10 ppm/c reference temperature range: C40c to +85c rail-to-rail output amplifier power-down mode package type: 100-lead lqfp (14 mm 14 mm) user interfaces: parallel serial (spi?/qspi?/microwire?/dsp compatible, featuring data readback) i 2 c? compatible integrated functions channel monitor simultaneous output update via ldac clear function to user programmable code amplifier boost mode to optimize slew rate user programmable offset and gain adjust toggle mode enables square wave generation thermal monitor applications variable optical attenuators (voa) level setting (ate) optical micro-electro-mechanical systems (mems) control systems instrumentation functional block diagram r r vout0 dac 0 dac reg 0 input reg 0 14 14 14 14 14 14 m reg 0 c reg 0 1.25v/2.5v reference power-on reset r r vout1 vout2 vout3 vout4 vout5 dac 1 dac reg 1 input reg 1 14 14 14 14 14 14 m reg 1 c reg 1 r r vout6 dac 6 dac reg 6 input reg 6 14 14 14 14 14 14 m reg 6 c reg 6 r r vout7 vout8 dac 7 dac reg 7 input reg 7 14 14 14 14 14 14 m reg 7 c reg 7 4 03733-0-001 fifo + state machine + control logic interface control logic db13/(din/sda) db12/(sclk/scl) db11/(spi/i2c) db10 a4 a0 reg 0 reg 1 reset busy clr mon_in1 mon_in2 mon_in3 mon_in4 pd ser/par fifo en cs/(sync/ad0) wr/(dcen/ad1) sdo 36-to-1 mux v out 0???v out 31 mon_out ldac vout31 dvdd (3) dgnd (3) avdd (4) agnd (4) dac gnd (4) refgnd refout/refin signal gnd (4) ad5382 db0 figure 1.
ad5382 rev. 0 | page 2 of 40 table of contents general description ......................................................................... 3 specifications..................................................................................... 4 ad5382-5 specifications ............................................................. 4 ad5382-3 specifications ............................................................. 6 ac characteristics........................................................................ 7 timing characteristics..................................................................... 8 spi, qspi, microwire, or dsp compatible serial interface .................................................................................... 8 i 2 c serial interface...................................................................... 10 parallel interface ......................................................................... 11 absolute maximum ratings.......................................................... 13 pin configuration and function descriptions........................... 14 terminology .................................................................................... 17 typical performance characteristics ........................................... 18 functional description .................................................................. 21 dac architecturegeneral..................................................... 21 data decoding ............................................................................ 21 on-chip special function registers (sfr) ............................ 22 sfr commands .......................................................................... 22 hardware functions....................................................................... 25 reset function ............................................................................ 25 asynchronous clear function.................................................. 25 busy and ldac functions...................................................... 25 fifo operation in parallel mode ............................................ 25 power-on reset.......................................................................... 25 power-down ............................................................................... 25 ad5382 interfaces.......................................................................... 26 dsp, spi, microwire compatible serial interfaces................. 26 i 2 c serial interface ..................................................................... 28 parallel interface......................................................................... 30 microprocessor interfacing....................................................... 31 application information................................................................ 33 power supply decoupling ......................................................... 33 typical configuration circuit .................................................. 33 ad5382 monitor function ....................................................... 34 toggle mode function............................................................... 34 thermal monitor function....................................................... 35 ad5382 in a mems based optical switch............................. 35 optical attenuators .................................................................... 36 outline dimensions ....................................................................... 37 ordering guide .......................................................................... 37 revision history 5/04revision 0: initial version
ad5382 rev. 0 | page 3 of 40 general description the ad5382 is a complete, single-supply, 32-channel, 14-bit dac available in a 100-lead lqfp package. all 32 channels have an on-chip output amplifier with rail-to-rail operation. the ad5382 includes an internal software-selectable 1.25 v/ 2.5 v, 10 ppm/c reference, an on-chip channel monitor function that multiplexes the analog outputs to a common mon_out pin for external monitoring, and an output amplifier boost mode that allows optimization of the amplifier slew rate. the ad5382 contains a double-buffered parallel interface that features a 20 ns wr pulse width, an spi/qspi/ microwire/dsp compatible serial interface with interface speeds in excess of 30 mhz and an i2c compatible interface that supports a 400 khz data transfer rate. an input register followed by a dac register provides double buffering, allowing the dac outputs to be updated indepen- dently or simultaneously using the ldac input. each channel has a programmable gain and offset adjust register that allows the user to fully calibrate any dac channel. power consumption is typically 0.25 ma/channel when operating with boost mode disabled. table 1. other high channel count, low voltag e, single supply dacs in product portfolio model resolution av dd range output channels linearity error (lsb) package description package option ad5380bst-5 14 bits 4.5 v to 5.5 v 40 4 100-lead lqfp st-100 ad5380bst-3 14 bits 2.7 v to 3.6 v 40 4 100-lead lqfp st-100 ad5384bbc-5 14 bits 4.5 v to 5.5 v 40 4 100-lead cspbga bc-100 ad5384bbc-3 14 bits 2.7 v to 3.6 v 40 4 100-lead cspbga bc-100 ad5381bst-5 12 bits 4.5 v to 5.5 v 40 1 100-lead lqfp st-100 ad5381bst-3 12 bits 2.7 v to 3.6 v 40 1 100-lead lqfp st-100 ad5383bst-5 12 bits 4.5 v to 5.5 v 32 1 100-lead lqfp st-100 ad5383bst-3 12 bits 2.7 v to 3.6 v 32 1 100-lead lqfp st-100 ad5390bst-5 14 bits 4.5 v to 5.5 v 16 3 52-lead lqfp st-52 ad5390bcp-5 14 bits 4.5 v to 5.5 v 16 3 64-lead lfcsp cp-64 ad5390bst-3 14 bits 2.7 v to 3.6 v 16 3 52-lead lqfp st-52 ad5390bcp-3 14 bits 2.7 v to 3.6 v 16 3 64-lead lfcsp cp-64 ad5391bst-5 12 bits 4.5 v to 5.5 v 16 1 52-lead lqfp st-52 ad5391bcp-5 12 bits 4.5 v to 5.5 v 16 1 64-lead lfcsp cp-64 ad5391bst-3 12 bits 2.7 v to 3.6 v 16 1 52-lead lqfp st-52 ad5391bcp-3 12 bits 2.7 v to 3.6 v 16 1 64-lead lfcsp cp-64 ad5392bst-5 14 bits 4.5 v to 5.5 v 8 3 52-lead lqfp st-52 ad5392bcp-5 14 bits 4.5 v to 5.5 v 8 3 64-lead lfcsp cp-64 ad5392bst-3 14 bits 2.7 v to 3.6 v 8 3 52-lead lqfp st-52 ad5392bcp-3 14 bits 2.7 v to 3.6 v 8 3 64-lead lfcsp cp-64 table 2. 40-channel bipolar voltage output dac model resolution analog supplies output channels linearity error (lsb) package package option ad5379abc 14 bits 11.4 v to 16.5 v 40 3 108-lead cspbga bc-108
ad5382 rev. 0 | page 4 of 40 specifications ad5382-5 specifications table 3. av dd = 4.5 v to 5.5 v; dv dd = 2.7 v to 5.5 v, agnd = dgnd = 0 v; external refin = 2.5 v; all specifications t min to t max , unless otherwise noted parameter ad5382-5 1 unit test conditions/comments accuracy resolution 14 bits relative accuracy 2 (inl) 4 lsb max differential nonlinearity (dnl) C1/+2 lsb max guaranteed monotonic over temperature zero-scale error 4 mv max offset error 4 mv max measured at code 32 in the linear region offset error tc 5 v/c typ gain error 0.024 % fsr max at 25c 0.06 % fsr max t min to t max gain temperature coefficient 3 2 ppm fsr/c typ dc crosstalk 3 0.5 lsb max reference input/output reference input 3 reference input voltage 2.5 v 1% for specified performance, avdd=2xrefin+50mv dc input impedance 1 m? min typically 100 m? input current 1 a max typically 30 na reference range 1 to v dd /2 v min/max reference output 4 enabled via cr10 in the ad5382 control register. cr12 selects the reference voltage. output voltage 2.495/2.505 v min/max at ambi ent. cr12 = 1. optimized for 2.5 v operation. 1.22/1.28 v min/max 1.25 v reference selected. cr12 = 0 reference tc 10 ppm/c max temperature range : +25c to +85c 15 ppm/c max temperature range : C40c to +85c output characteristics 3 output voltage range 2 0/av dd v min/max short-circuit current 40 ma max load current 1 ma max capacitive load stability r l = 200 pf max r l = 5 k? 1000 pf max dc output impedance 0.5 ? max monitor pin output impedance 500 ? typ three-state leakage current 100 na typ logic inputs (except sda/scl) 3 dv dd = 2.7 v to 5.5 v v ih , input high voltage 2 v min v il , input low voltage 0.8 v max input current 10 a max total for all pins. t a = t min to t max pin capacitance 10 pf max logic inputs (sda, scl only) v ih , input high voltage 0.7 dv dd v min smbus compatible at dv dd < 3.6 v v il , input low voltage 0.3 dv dd v max smbus compatible at dv dd < 3.6 v i in , input leakage current 1 a max v hyst , input hysteresis 0.05 dv dd v min c in , input capacitance 8 pf typ glitch rejection 50 ns max input filtering suppresses noise spikes of less than 50 ns
ad5382 rev. 0 | page 5 of 40 parameter ad5382-5 1 unit test conditions/comments logic outputs (busy , sdo) 3 v ol , output low voltage 0.4 v max dv dd = 5 v 10%, sinking 200 a v oh , output high voltage dv dd C 1 v min dv dd = 5 v 10%, sourcing 200 a v ol , output low voltage 0.4 v max dv dd = 2.7 v to 3.6 v, sinking 200 a v oh , output high voltage dv dd C 0.5 v min dv dd = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current 1 a max sdo only high impedance output capacitance 5 pf typ sdo only logic output (sda) 3 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma three-state leakage current 1 a max three-state output capacitance 8 pf typ power requirements av dd 4.5/5.5 v min/max dv dd 2.7/5.5 v min/max power supply sensitivity 3 ?mid scale/?v dd C85 db typ ai dd 0.375 ma/channel max outputs un loaded, boost off. 0.25 ma/channel typ 0.475 ma/channel max outputs unlo aded, boost on. 0.325 ma/channel typ di dd 1 ma max v ih = dv dd , v il = dgnd. ai dd (power-down) 2 a max typically 200 na di dd (power-down) 20 a max typically 3 a power dissipation 65 mw max o utputs unloaded, boost off, av dd = dv dd = 5 v 1 ad5382-5 is calibrated using an extern al 2.5 v reference. temp erature range for all vers ions: C40c to +85c. 2 accuracy guaranteed from v out = 10 mv to av dd C 50 mv. 3 guaranteed by characterization, not production tested. 4 default on the ad5382-5 is 2.5 v. programmable to 1.25 v via cr12 in the ad5382 control register; operating the ad5382-5 with a 1.25 v reference leads to degraded accuracy specifications.
ad5382 rev. 0 | page 6 of 40 ad5382-3 specifications table 4. av dd = 2.7 v to 3.6 v; dv dd = 2.7 v to 5.5 v, agnd = dgnd = 0 v; external refin = 1.25 v; all specifications t min to t max , unless otherwise noted parameter ad5382-3 1 unit test conditions/comments accuracy resolution 14 bits relative accuracy 2 (inl) 4 lsb max differential nonlinearity (dnl) C1/+2 lsb max guaranteed monotonic over temperature zero-scale error 4 mv max offset error 4 mv max measured at code 64 in the linear region offset error tc 5 v/c typ gain error 0.024 % fsr max at 25 c 0.06 % fsr max t min to t max gain temperature coefficient 3 2 ppm fsr/c typ dc crosstalk 3 0.5 lsb max reference input/output reference input 3 reference input voltage 1.25 v 1% for specified performance dc input impedance 1 m? min typically 100 m? input current 10 a max typically 30 na reference range 1 to av dd /2 v min/max reference output 4 enabled via cr10 in the ad5382 control register. cr12 selects the reference voltage. output voltage 1.247/1.253 v min/max at ambien t. cr12 = 0. optimized for 1.25 v operation 2.43/2.57 v min/max 2.5 v reference selected, cr12 = 1 reference tc 10 ppm/c max temperature range : +25c to +85c 15 ppm/c max temperature range :C40c to +85c output characteristics 3 output voltage range 2 0/av dd v min/max short-circuit current 40 ma max load current 1 ma max capacitive load stability r l = 200 pf max r l = 5 k? 1000 pf max dc output impedance 0.5 ? max monitor pin (mon out) output impedance 500 ? typ three-state leakage current 100 na typ logic inputs (except sda/scl) 3 dv dd = 2.7 v to 3.6 v v ih , input high voltage 2 v min v il, input low voltage 0.8 v max input current 10 a max total for all pins. t a = t min to t max pin capacitance 10 pf max logic inputs (sda, scl only) v ih , input high voltage 0.7 dv dd v min smbus compatible at dv dd < 3.6 v v il , input low voltage 0.3 dv dd v max smbus compatible at dv dd < 3.6 v i in , input leakage current 1 amax v hyst , input hysteresis 0.05 dv dd v min c in , input capacitance 8 pf typ glitch rejection 50 ns max input filtering su ppresses noise spikes of less than 50 ns
ad5382 rev. 0 | page 7 of 40 parameter ad5382-3 1 unit test conditions/comments logic outputs (busy , sdo) 3 v ol , output low voltage 0.4 v max sinking 200 a v oh , output high voltage dv dd C 0.5 v min sourcing 200 a high impedance leakage current 1 a max sdo only high impedance output capacitance 5 pf typ sdo only logic output (sda) 3 v ol , output low voltage 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma three-state leakage current 1 a max three-state output capacitance 8 pf typ power requirements av dd 2.7/3.6 v min/max dv dd 2.7/5.5 v min/max power supply sensitivity 3 ?midscale/?v dd C85 db typ ai dd 0.375 ma/channel max outputs unlo aded, boost off. 0.25 ma/channel typ 0.475 ma/channel max outputs unlo aded, boost on. 0.325 ma/channel typ di dd 1 ma max v ih = dv dd , v il = dgnd. ai dd (power-down) 2 a max di dd (power-down) 20 a max power dissipation 39 mw max o utputs unloaded, boost off, av dd = dv dd = 3 v 1 ad5382-3 is calibrated using an external 1.25 v reference. temper ature range is C 40c to +85c. 2 accuracy guaranteed from v out = 10 mv to av dd C 50 mv. 3 guaranteed by characterization, not production tested. 4 default on the ad5382-5 is 2.5 v. programmable to 1.25 v via cr12 in the ad5382 control register; operating the ad5382-5 with a 1.25 v reference leads to degraded accuracy specifications. ac characteristics 1 table 5. av dd = 4.5 v to 5.5 v; dv dd = 2.7 v to 5.5 v; agnd = dgnd= 0 v parameter all unit test conditions/comments dynamic performance output voltage settling time 2 1/4 scale to 3/4 scale change settling to 1 lsb. 8 s typ 10 s max slew rate 2 2 v/s typ boost mode off, cr11 = 0 3 v/s typ boost mode on, cr11 = 1 digital-to-analog glitch energy 12 nv-s typ glitch impulse peak amplitude 15 mv typ channel-to-channel isolation 100 db typ see terminology section dac-to-dac crosstalk 1 nv-s typ see terminology section digital crosstalk 0.8 nv-s typ digital feedthrough 0.1 nv-s typ effect of input bus activity on dac output under test output noise 0.1 hz to 10 hz 15 v p-p typ ex ternal reference, midscale loaded to dac 40 v p-p typ internal refere nce, midscale loaded to dac output noise spectr al density @ 1 khz 150 nv/hz typ @ 10 khz 100 nv/hz typ 1 guaranteed by design and characterization, not production tested. 2 the slew rate can be programmed via the current boos t control bit (cr11 ) in the ad5382 control register.
ad5382 rev. 0 | page 8 of 40 timing characteristics spi, qspi, microwire, or dsp compatible serial interface table 6. dv dd = 2.7 v to 5.5 v ; av dd = 4.5 v to 5.5 v or 2.7 v to 3.6 v; agnd = dgnd = 0 v; all specifications t min to t max , unless otherwise noted parameter 1 , 2 , 3 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 4 13 ns min 24th sclk falling edge to sync falling edge t 6 4 33 ns min minimum sync low time t 7 10 ns min minimum sync high time t 7a 50 ns min minimum sync high time in readback mode t 8 5 ns min data setup time t 9 4.5 ns min data hold time t 10 4 30 ns max 24th sclk falling edge to busy falling edge t 11 670 ns max busy pulse width low (single channel update) t 12 4 20 ns min 24th sclk falling edge to ldac falling edge t 13 20 ns min ldac pulse width low t 14 100 ns max busy rising edge to dac output response time t 15 0 ns min busy rising edge to ldac falling edge t 16 100 ns min ldac falling edge to dac output response time t 17 8 s typ dac output settling time t 18 20 ns min clr pulse width low t 19 35 s max clr pulse activation time t 20 5 20 ns max sclk rising edge to sdo valid t 21 5 5 ns min sclk falling edge to sync rising edge t 22 5 8 ns min sync rising edge to sclk rising edge t 23 20 ns min sync rising edge to ldac falling edge 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of v cc ) and are timed from a voltage level of 1.2 v. 3 see figure 2, figure 3, figure 4, and figure 5. 4 standalone mode only. 5 daisy-chain mode only. c l 50pf t o output pin v oh (min) or v ol (max) 200 a 200 a i ol i oh 03731-0-003 figure 2. load circuit for sdo timing diagram (serial interface, daisy-chain mode)
ad5382 rev. 0 | page 9 of 40 1 ldac active during busy 2 ldac active after busy busy sync ldac 1 ldac 2 clr v out v out 2 v out 1 din sclk 03731-0-004 t 7 t 8 t 9 t 4 t 3 t 1 t 2 t 5 t 17 t 17 t 12 t 13 t 18 t 19 t 16 t 14 t 10 t 15 t 13 t 11 t 6 db0 db23 24 24 figure 3. serial interface timing diagram (standalone mode) t 7a 24 48 sclk sync din sdo db23 db0 db23 db0 db23 db0 input word specifies register to be read undefined nop condition selected register data clocked out 03731-0-005 figure 4. serial interface timing diagram (data readback mode) t 22 t 13 t 23 t 21 t 2 t 3 t 20 t 8 t 9 t 7 t 4 t 1 sclk sync sdo din ldac 48 24 db23 db0 db0 db23 db23 db0 input word for dac n input word for dac n+1 undefined input word for dac n 03731-0-006 figure 5. serial interface timing diagram (daisy-chain mode)
ad5382 rev. 0 | page 10 of 40 i 2 c serial interface table 7. dv dd = 2.7 v to 5.5 v; av dd = 4.5 v to 5.5 v or 2.7 v to 3.6 v; agnd = dgnd = 0 v; all specifications t min to t max , unless otherwise noted parameter 1 , 2 limit at t min , t max unit description f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat , data setup time t 6 3 0.9 s max t hd,dat , data hold time 0 s min t hd,dat , data hold time t 7 0.6 s min t su,sta , setup time for repeated start t 8 0.6 s min t su,sto , stop condition setup time t 9 1.3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t r , rise time of scl and sda when receiving 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 300 ns max t f , fall time of sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 300 ns max t f , fall time of scl and sda when receiving 20 + 0.1c b 4 ns min t f , fall time of scl and sda when transmitting c b 400 pf max capacitive load for each bus line 1 guaranteed by design and characterization, not production tested. 2 see figure 6. 3 a master device must provide a ho ld time of at least 300 ns for the sda signal (ref erred to the v ih min of the scl signal) in order to bridge the undefined region of scls falling edge. 4 c b is the total capacitance, in pf, of one bus line. t r and t f are measured between 0.3 dv dd and 0.7 dv dd . start condition repeated start condition stop condition t 9 t 3 t 1 t 11 t 4 t 10 t 4 t 5 t 7 t 6 t 8 t 2 sda scl 03731-0-007 figure 6. i2c compatible serial interface timing diagram
ad5382 rev. 0 | page 11 of 40 parallel interface table 8. dv dd = 2.7 v to 5.5 v; av dd = 4.5 v to 5.5 v or 2.7 v to 3.6 v; agnd = dgnd = 0 v; all specifications t min to t max , unless otherwise noted parameter 1 , 2 , 3 limit at t min , t max unit description t 0 4.5 ns min reg0, reg1, address to wr rising edge setup time t 1 4.5 ns min reg0, reg1, address to wr rising edge hold time t 2 20 ns min cs pulse width low t 3 20 ns min wr pulse width low t 4 0 ns min cs to wr falling edge setup time t 5 0 ns min wr to cs rising edge hold time t 6 4.5 ns min data to wr rising edge setup time t 7 4.5 ns min data to wr rising edge hold time t 8 20 ns min wr pulse width high t 9 4 700 ns min minimum wr cycle time (single-channel write) t 10 4 30 ns max wr rising edge to busy falling edge t 11 4, 5 670 ns max busy pulse width low (single-channel update) t 12 30 ns min wr rising edge to ldac falling edge t 13 20 ns min ldac pulse width low t 14 100 ns max busy rising edge to dac output response time t 15 20 ns min ldac rising edge to wr rising edge t 16 0 ns min busy rising edge to ldac falling edge t 17 100 ns min ldac falling edge to dac output response time t 18 8 s typ dac output settling time t 19 20 ns min clr pulse width low t 20 35 smax clr pulse activation time 1 guaranteed by design and characterization, not production tested. 2 all input signals are specified with t r = t r = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.2 v. 3 see figure 7. 4 see figure 29. 5 measured with the load circuit of figure 2.
ad5382 rev. 0 | page 12 of 40 t 18 t 18 t 19 t 20 t 13 t 3 t 2 t 8 t 13 t 11 t 9 t 12 t 0 t 1 t 15 t 7 t 6 t 17 t 16 t 10 t 14 t 4 t 5 reg0, reg1, a4..a0 cs wr db13..db0 busy ldac 1 v out 1 v out 2 clr v out ldac 2 1 ldac active during busy 2 ldac active after busy 03731-0-008 figure 7. parallel interface timing diagram
ad5382 rev. 0 | page 13 of 40 absolute maximum ratings table 9. t a = 25c, unless otherwise noted 1 parameter rating av dd to agnd C0.3 v to +7 v dv dd to dgnd C0.3 v to +7 v digital inputs to dgnd C0.3 v to dv dd + 0.3 v sda/scl to dgnd C0.3 v to + 7 v digital outputs to dgnd C0.3 v to dv dd + 0.3 v refin/refout to agnd C0.3 v to av dd + 0.3 v agnd to dgnd C0.3 v to +0.3 v voutx to agnd C0.3 v to av dd + 0.3 v analog inputs to agnd C0.3 v to av dd + 0.3 v mon_in inputs to agnd C0.3 v to av dd + 0.3 v mon_out to agnd C0.3 v to av dd + 0.3 v operating temperature range commercial (b version) C40c to +85c storage temperature range C65c to +150c junctiontemperature (t j max) 150c 100-lead lqfp package ja thermal impedance 44c/w reflow soldering peak temperature 230c 1 transient currents of up to 100 ma will not cause scr latch-up stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discha rges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5382 rev. 0 | page 14 of 40 pin configuration and fu nction descriptions reset db7 db6 db5 db4 db3 db2 db1 db0 reg0 reg1 vout23 vout22 vout21 vout20 avdd3 agnd3 dac_gnd3 signal_gnd3 vout19 vout18 vout17 vout16 avdd2 agnd2 59 74 75 69 70 71 72 67 68 66 73 64 65 60 61 62 63 57 58 55 56 53 54 52 51 nc nc nc nc vout5 vout6 vout7 nc nc mon_in1 mon_in2 mon_in3 mon_in4 nc mon_out vout8 vout9 vout10 vout11 vout12 dac_gnd2 signal_gnd2 vout13 vout14 vout15 26 28 27 29 30 32 33 34 35 36 31 37 38 39 40 42 43 44 45 41 46 47 48 49 50 cs/(sync/ad0) db13/(din/sda) db12/(sclk/scl) db11/(spi/i2c) db10 db9 db8 sdo(a/b) dvdd dgnd dgnd nc a4 a3 a2 a1 a0 dvdd dvdd dgnd ser/par pd wr (dcen/ad1) ldac busy 100 98 99 97 96 95 94 92 91 90 89 88 87 93 86 85 84 82 81 80 79 78 77 76 83 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 24 25 fifo en clr vout24 vout25 vout26 vout27 signal_gnd4 dac_gnd4 agnd4 avdd4 vout28 vout29 vout30 vout31 ref gnd refout/refin signal_gnd1 dac_gnd1 avdd1 vout0 vout1 vout2 vout3 vout4 agnd1 pin 1 identifier ad5382 top view (not to scale) 03733-0-002 figure 8. 100-lead lqfp pin configuration table 10. pin function descriptions mnemonic function voutx buffered analog outputs for channel x. ea ch analog output is driven by a rail-t o-rail output amplifier operating at a gain of 2. each output is capable of driving an output load of 5 k? to grou nd. typical output impedance is 0.5 ?. signal_gnd(1C4) analog ground reference points for ea ch group of eight output channels. a ll signal_gnd pins are tied together internally and should be connected to the ag nd plane as close as possible to the ad5382. dac_gnd(1C4) each group of eight channels contains a dac_gnd pin. th is is the ground reference point for the internal 14-bit dac. these pins shound be connected to the agnd plane. agnd(1C4) analog ground reference point. each group of eight cha nnels contains an agnd pin. all agnd pins should be connected externally to the agnd plane. avdd(1C4) analog supply pins. each group of eight channels has a separate avdd pin. these pins are internally shorted and should be decoupled with a 0.1 f ceramic capacitor and a 10 f tantalum capaci tor. operating range for the ad5382-5 is 4.5 v to 5.5 v; operating ra nge for the ad5382-3 is 2.7 v to 3.6 v. dgnd ground for all digital circuitry. dvdd logic power supply. guaranteed operating range is 2.7 v to 5.5 v. it is reco mmended that these pins be decoupled with 0.1 f ceramic and 10 f tantalum capacitors to dgnd. refgnd ground reference poin t for the internal reference. refout/refin the ad5382 contains a common refout/refin pin. when the in ternal reference is selected, this pin is the reference output. if the application requires an ex ternal reference, it can be applied to this pin and the internal reference can be disabled via the control register. the de fault for this pin is a reference input. mon_out when the monitor function is enabled, this pin acts as the output of a 36- to-1 channel multiplexer that can be programmed to multiplex one of channels 0 to 31 or any of the monitor input pins (mo n_in1 to mon_in4) to the mon_out pin. the mon_out pins outp ut impedance is typically 500 ? and is intended to drive a high input impedance like that exhibited by sar adc inputs.
ad5382 rev. 0 | page 15 of 40 mnemonic function mon_inx monitor input pins. the ad5382 cont ains four monitor input pins that allow th e user to connect input signals, within the maximum ratings of the device, to these pins for monito ring purposes. any of the signals applied to the mon_in pins along with the 32 output channels ca n be switched to the mon_out pin via software. for example, an external adc can be used to monitor these signals. ser/par interface select input. this pin allows the user to select wh ether the serial or parallel interface will be used. if it is ti ed high, the serial interface mode is selected and pin 97 (spi /i2c) is used to determine if the interface mode is spi or i 2 c. parallel interface mode is selected when ser/par is low. cs /(sync /ad0) in parallel interface mode , this pin acts as the chip select input (level sensitive, active low). when low, the ad5382 is selected. in serial interface mode, this is the frame synchronizatio n input signal for the serial clocks before the addressed register is updated. in i 2 c mode, this pin acts as a hardware address pin used in conjunction with ad1 to determine the software address for the device on the i 2 c bus. wr /(dcen/ ad1) multifunction pin. in parallel interface mode, this pin acts as write en able. in serial interface mode, this pin a cts as a daisy-chain enable in spi mode and as a hardware address pin in i 2 c mode. parallel interface write input (edge sensitive). the rising edge of wr is used in conjunction with cs low and the address bus inputs to write to the selected device registers. serial interface. daisy-chain select input (level sensitive, ac tive high). when high, this si gnal is used in conjunction with ser/par high to enable the spi serial interface daisy-chain mode. i 2 c mode. this pin acts as a hardware address pin used in conjunction with ad0 to determine the software address for this device on the i 2 c bus. db13Cdb0 parallel data bus. db13 is the msb and db 0 is the lsb of the input data-word on the ad5382. a4Ca0 parallel address inputs. a4 to a0 are decoded to address one of the ad5382s 40 input channels. used in conjunction with the reg1 and reg0 pins to determine the destination register for the input data. reg1, reg0 in parallel interface mode, reg1 and re g0 are used in decoding the destinat ion registers for the input data. reg1 and reg0 are decoded to addre ss the input data register, offset register, or gain register for the selected channel and are also used to decide the special function registers. sdo/(a /b) serial data output in seri al interface mode. three-stateable cmos outp ut. sdo can be used for daisy-chaining a number of devices together. data is clocked out on sdo on the rising edge of sclk, and is valid on the falling edge of sclk. in parallel interface mode, this pin ac ts as the a or b data register select when writing data to the ad5382s data registers with toggle mode selected (see the toggle mode function section). in toggle mode, the ldac is used to switch the output between the data cont ained in the a and b data registers. all dac channels contain two data registers. in normal mode, data register a is the default for data transfers. busy digital cmos output. busy goes low during internal calc ulations of the data (x2) load ed to the dac data register. during this time, the user can continue writing new data to the x1, c, and m re gisters, but no further updates to the dac registers and dac outputs can take place. if ldac is taken low while busy is low, this event is stored. busy also goes low during power-on reset, and when the reset pin is low. during this time, the interface is disabled and any events on ldac are ignored. a clr operation also brings busy low. ldac load dac logic input (active low). if ldac is taken low while busy is inactive (high), the contents of the input registers are transferred to the dac register s and the dac outputs are updated. if ldac is taken low while busy is active and internal calculations are taking place, the ldac event is stored and the dac registers are updated when busy goes inactive. however any events on ldac during power-on reset or on reset are ignored. clr asynchronous clea r input. the clr input is falli ng edge sensitive. when clr is activated, all channels are updated with the data contained in the clr code register. busy is low for a duration of 35 s while all channels are being updated with the clr code. reset asynchronous digital reset inp ut (falling edge sensitive). the function of th is pin is equivalent to that of the power- on reset generator. when this pin is taken low, the state ma chine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values . this sequence takes 270 s. the falling edge of reset initiates the reset process and busy goes low for the duration, returning high when reset is complete. while busy is low, all interfaces are disabled and all ldac pulses are ignored. when busy returns high, the part resumes normal operation and the status of the reset pin is ignored until the next falling edge is detected. pd power down (level sensitive, active high ). pd is used to place the device in low power mode where the device consumes 2 a aidd and 20 a didd. in power-down mode, a ll internal analog circuitry is placed in low power mode, and the analog output will be configured as a hi gh impedance output or will provide a 100 k? load to ground, depending on how the power-down mode is config ured. the serial interface remains active during power- down.
ad5382 rev. 0 | page 16 of 40 mnemonic function fifoen fifo enable (level sensitive, active high ). when connected to dvdd, the internal fifo is enabled, allowing the user to write to the device at full speed. fifo is only availabl e in parallel interface mode. the status of the fifo_en pin is sampled on power-up, and also following a clear or reset, to determine if the fifo is enabled. in either serial or i 2 c interface modes, the fifo_en pin should be tied low. db11 (spi /i2c) multifunction input pin. in parallel interface mode, this pin acts as db11 of the parallel input data-word. in serial interface mode, this pin acts as serial interface mode select. when serial interface mode is selected (ser/par = 1) and this input is low, spi mode is selected . in spi mode, db12 is the serial clock (s clk) input and db13 is the serial data (din) input. when serial interface mode is selected (ser/par = 1) and this input is high i 2 c mode is selected. in this mode, db12 is the serial clock (scl) input and db13 is the serial data (sda) input. db12 (sclk/scl) multifunction input pin. in parallel in terface mode, this pin acts as db12 of the parallel input data-word. in serial interface mode, this pin acts as a serial clock input. serial interface mode. in serial interface mode, data is clocked into the shift register on the falling edge of sclk. this operates at clock speeds up to 50 mhz. i 2 c mode. in i 2 c mode, this pin performs the scl function, clocking data into the device. the data transfer rate in i 2 c mode is compatible with both 100 khz and 400 khz operating modes. db13/(din/sda) multifunction data input pin. in parallel interface mode, this pin acts as db13 of the para llel input data-word . serial interface mode. in serial interface mode, this pin acts as the serial data input. data mu st be valid on the falling edge of sclk. i 2 c mode. in i 2 c mode, this pin is the serial data pin (s da) operating as an open-drain input/output. nc no connect. the user is advised not to connect any signals to these pins.
ad5382 rev. 0 | page 17 of 40 terminology relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error, and is expressed in lsb. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. zero-scale error zero-scale error is the error in the dac output voltage when all 0s are loaded into the dac register. ideally, with all 0s loaded to the dac and m = all 1s, c = 2 n C 1 : vout ( zero-scale ) = 0 v zero-scale error is a measure of the difference between vout (actual) and vout (ideal), expressed in mv. it is mainly due to offsets in the output amplifier. offset error offset error is a measure of the difference between vout (actual) and vout (ideal) in the linear region of the transfer function, expressed in mv. offset error is measured on the ad5382-5 with code 32 loaded into the dac register, and on the ad5382-3 with code 64. gain error gain error is specified in the linear region of the output range between v out = 10 mv and v out = av dd C 50 mv. it is the deviation in slope of the dac transfer characteristic from the ideal and is expressed in %fsr with the dac output unloaded. dc crosstalk this is the dc change in the output level of one dac at midscale in response to a full-scale code (all 0s to all 1s, and vice versa) and output change of all other dacs. it is expressed in lsb. dc output impedance this is the effective output source resistance. it is dominated by package lead resistance. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full-scale input change, and is measured from the busy rising edge. digital-to-analog glitch energy this is the amount of energy injected into the analog output at the major code transition. it is specified as the area of the glitch in nv-s. it is measured by toggling the dac register data between 0x1fff and 0x2000. dac-to-dac crosstalk dac-to-dac crosstalk is the glitch impulse that appears at the output of one dac due to both the digital change and to the subsequent analog output change at another dac. the victim channel is loaded with midscale. dac-to-dac crosstalk is specified in nv-s. digital crosstalk the glitch impulse transferred to the output of one converter due to a change in the dac register code of another converter is defined as the digital crosstalk and is specified in nv-s. digital feedthrough when the device is not selected, high frequency logic activity on the devices digital inputs can be capacitively coupled both across and through the device to show up as noise on the vout pins. it can also be coupled along the supply and ground lines. this noise is digital feedthrough. output noise spectral density this is a measure of internally generated random noise. random noise is characterized as a spectral density (voltage per hertz). it is measured by loading all dacs to midscale and measuring noise at the output. it is measured in nv/hz in a 1 hz bandwidth at 10 khz.
ad5382 rev. 0 | page 18 of 40 typical performance characteristics 03731-0-033 input code 16384 0 4096 8192 12288 inl error (lsb) ?2.0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 av dd = dv dd = 5.5v v ref = 2.5v t a = 25c figure 9. typical ad5382-5 inl plot 03731-0-034 sample number 550 0 100 150 200 250 300 50 350 400 500 450 amplitude (v) 2.523 2.539 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 av dd = dv dd = 5v v ref = 2.5v t a = 25c 14ns/sample number 1 lsb change around midscale glitch impulse = 10nv-s figure 10. ad5382-5 glitch impulse 03732-0-003 av dd = dv dd = 5v v ref = 2.5v t a = 25c v out figure 11. slew rate with boost off 03731-0-035 input code 16384 0 4096 8192 12288 inl error (lsb) ?2.0 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 av dd = dv dd = 3v v ref = 1.25v t a = 25c figure 12. typical ad5382-3 inl plot 03731-0-036 sample number 550 0 100 150 200 250 300 50 350 400 500 450 amplitude (v) 1.245 1.254 1.253 1.252 1.251 1.250 1.249 1.248 1.247 1.246 av dd = dv dd = 3v v ref = 1.25v t a = 25c 14ns/sample number 1 lsb change around midscale glitch impulse = 5nv-s figure 13. ad5382-3 glitch impulse 03732-0-004 av dd = dv dd = 5v v ref = 2.5v t a = 25c v out figure 14. slew rate with boost on
ad5382 rev. 0 | page 19 of 40 04598-0-049 ai dd (ma) 11 8910 percentage of units (%) 14 12 10 8 6 4 2 av dd = 5.5v v ref = 2.5v t a = 25c figure 15. ai dd histogram 04598-0-050 di dd (ma) 0.8 0.9 0.4 0.5 0.6 0.7 number of units 0 10 8 6 4 2 dv dd = 5.5v v ih = dv dd v il = dgnd t a = 25c figure 16. di dd histogram 03731-0-045 av dd = dv dd = 5v v ref = 2.5v t a = 25c exits soft pd to midscale v out busy wr figure 17. exiting soft power down 03731-0-011 av dd = dv dd = 5v v ref = 2.5v t a = 25c power supply ramp rate = 10ms v out av dd figure 18. ad5382 power-up transient 04598-0-051 inl error distribution (lsb) 2 ?2 ?1 0 1 number of units 0 14 12 10 8 6 4 2 av dd = 5.5v refin = 2.5v t a = 25c figure 19. inl error distribution 03731-0-038 av dd = dv dd = 5v v ref = 2.5v t a = 25c exits hardware pd to midscale pd v out figure 20. exiting hardware power down
ad5382 rev. 0 | page 20 of 40 03731-0-039 current (ma) ?40 ?20 ?10 ?5 ?2 0 2 5 10 20 40 v out (v) ?1 6 4 3 2 5 1 0 zeroscale 1/4 scale midscale 3/4 scale fullscale av dd = dv dd = 5v v ref = 2.5v t a = 25c figure 21. ad5382-5 output amplifier source and sink capability 03731-0-047 i source /i sink (ma) 2.00 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 error voltage (v) ?0.20 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.15 av dd = 5v v ref = 2.5v t a = 25c error at zero sinking current (v dd ?v out ) at full-scale sourcing current figure 22. headroom at rails vs. source/sink current 03731-0-047 frequency (hz) 100k 100 1k 10k output noise (nv/ hz) 0 600 500 400 300 200 100 av dd = 5v t a = 25c refout decoupled with 100nf capacitor refout = 2.5v refout = 1.25v figure 23 refout noise spectral density 03731-0-040 current (ma) ?40 ?20 ?10 ?5 ?2 0 2 5 10 20 ?40 v out (v) ?1 6 4 3 2 5 1 0 zero-scale 1/4 scale midscale 3/4 scale full-scale av dd = dv dd = 3v v ref = 1.25v t a = 25c figure 24. ad5382-3 output amplifier source and sink capability 03731-0-041 sample number 550 0 100 150 200 250 300 50 350 400 500 450 amplitude (v) 2.449 2.456 2.455 2.454 2.453 2.452 2.451 2.450 av dd = dv dd = 5v v ref = 2.5v t a = 25c 14ns/sample number figure 25. adjacent channel dac-to-dac crosstalk av dd = dv dd = 5v v ref = 2.5v t a = 25c exits soft pd to midscale 03731-0-046 av dd = dv dd = 5v t a = 25c dac loaded with midscale external reference y axis = 5 v/div x axis = 100ms/div figure 26. 0.1 hz to 10 hz noise plot
ad5382 rev. 0 | page 21 of 40 functional description dac architecturegeneral the ad5382 is a complete, single-supply, 32-channel voltage output dac that offers 14-bit resolution. the part is available in a 100-lead lqfp package and features both a parallel and a serial interface. this product includes an internal, software selectable, 1.25 v/2.5 v, 10 ppm/c reference that can be used to drive the buffered reference inputs; alternatively, an external reference can be used to drive these inputs. internal/external reference selection is via the cr10 bit in the control register; cr12 selects the reference magnitude if the internal reference is selected. all channels have an on-chip output amplifier with rail-to-rail output capable of driving 5 k? in parallel with a 200 pf load. 03731-0-016 v out r r 14-bit dac dac reg m reg c reg 1 input reg 2 input dat a v ref avdd figure 27. single-channel architecture the architecture of a single dac channel consists of a 14-bit resistor-string dac followed by an output buffer amplifier operating at a gain of 2. this resistor-string architecture guarantees dac monotonicity. the 14-bit binary digital code loaded to the dac register determines at what node on the string the voltage is tapped off before being fed to the output amplifier. each channel on these devices contains independent offset and gain control registers that allow the user to digitally trim offset and gain. these registers give the user the ability to calibrate out errors in the complete signal chain, including the dac, using the internal m and c registers, which hold the correction factors. all channels are double buffered, allowing synchronous updating of all channels using the ldac pin. figure 27 shows a block diagram of a single channel on the ad5382. the digital input transfer function for each dac can be represented as x2 = [( m + 2)/ 2 n x1 ] + ( c C 2 n C 1 ) where: x2 is the data-word loaded to the resistor string dac. x1 is the 14-bit data-word written to the dac input register. m is the gain coefficient (default is 0x3ffe on the ad5382). the gain coefficient is written to the 13 most significant bits (db13 to db1) and lsb (db0) is a zero. n = dac resolution ( n = 14 for ad5382). c is the14-bit offset coefficient (default is 0x2000). the complete transfer function for these devices can be represented as v out = 2 v ref x2 /2 n x2 is the data-word loaded to the resistor string dac. v ref is the internal reference voltage or the reference voltage externally applied to the dac refout/refin pin. for specified performance, an external reference voltage of 2.5 v is recommended for the ad5380-5, and 1.25 v for the ad5380-3. data decoding the ad5382 contains a 14-bit data bus, db13Cdb0. depending on the value of reg1 and reg0 (see table 11), this data is loaded into the addressed dac input registers, offset (c) registers, or gain (m) registers. the format data, offset (c), and gain (m) register contents are shown in table 12 to table 14. table 11. register selection reg1 reg0 register selected 1 1 input data register (x1) 1 0 offset register (c) 0 1 gain register (m) 0 0 special function registers (sfrs) table 12. dac data format (reg1 = 1, reg0 = 1) db13 to db0 dac output (v) 11 1111 1111 1111 2 v ref (16383/16384) 11 1111 1111 1110 2 v ref (16382/16384) 10 0000 0000 0001 2 v ref (8193/16384) 10 0000 0000 0000 2 v ref (8192/16384) 01 1111 1111 1111 2 v ref (8191/16384) 00 0000 0000 0001 2 v ref (1/16384) 00 0000 0000 0000 0 table 13. offset data format (reg1 = 1, reg0 = 0) db13 to db0 offset (lsb) 11 1111 1111 1111 +8191 11 1111 1111 1110 +8190 10 0000 0000 0001 +1 10 0000 0000 0000 0 01 1111 1111 1111 C1 00 0000 0000 0001 C8191 00 0000 0000 0000 C8192 table 14. gain data format (reg1 = 0, reg0 = 1) db13 to db0 gain factor 11 1111 1111 1110 1 10 1111 1111 1110 0.75 01 1111 1111 1110 0.5 00 0111 1111 1110 0.25 00 0000 0000 0000 0
ad5382 rev. 0 | page 22 of 40 on-chip special function registers (sfr) the ad5382 contains a number of special function registers (sfrs), as outlined in table 15. sfrs are addressed with reg1 = reg0 = 0 and are decoded using address bits a4 to a0. table 15. sfr register functions (reg1 = 0, reg0 = 0) r/ w a4 a3 a2 a1 a0 function x 0 0 0 0 0 nop (no operation) 0 0 0 0 0 1 write clr code 0 0 0 0 1 0 soft clr 0 0 1 0 0 0 soft power-down 0 0 1 0 0 1 soft power-up 0 0 1 1 0 0 control register write 1 0 1 1 0 0 control register read 0 0 1 0 1 0 monitor channel 0 0 1 1 1 1 soft reset sfr commands nop (no operation) reg1 = reg0 = 0, a4Ca0 = 00000 performs no operation but is useful in serial readback mode to clock out data on d out for diagnostic purposes. busy pulses low during a nop operation. write clr code reg1 = reg0 = 0, a4Ca0 = 00001 db13Cdb0 = contain the clr data bringing the clr line low or exercising the soft clear function will load the contents of the dac registers with the data con- tained in the user configurable clr register, and will set vout0 to vout31 accordingly. this can be very useful for setting up a specific output voltage in a clear condition. it is also beneficial for calibration purposes; the user can load full scale or zero scale to the clear code register and then issue a hard- ware or software clear to load this code to all dacs, removing the need for individual writes to each dac. default on power- up is all zeros. soft clr reg1 = reg0 = 0, a4Ca0 = 00010 db13Cdb0 = dont care. executing this instruction performs the clr, which is function- ally the same as that provided by the external clr pin. the dac outputs are loaded with the data in the clr code register. it takes 35 s to fully execute the soft clr and is indicated by the busy low time. soft power-down reg1 = reg0 = 0, a4Ca0 = 01000 db13Cdb0 = dont care executing this instruction performs a global power-down feature that puts all channels into a low power mode that reduces the analog supply current to 2 a max and the digital current to 20 a max. in power-down mode, the output amplifier can be configured as a high impedance output or provide a 100 k? load to ground. the contents of all internal registers are retained in power-down mode. no register can be written to while in power-down. soft power-up reg1 = reg0 = 0, a4Ca0 = 01001 db13Cdb0 = dont care this instruction is used to power up the output amplifiers and the internal reference. the time to exit powerCdown is 8 s. the hardware power-down and software function are internally combined in a digital or function. soft reset reg1 = reg0 = 0, a4Ca0 = 01111 db13Cdb0 = dont care this instruction is used to implement a software reset. all internal registers are reset to their default values, which correspond to m at full scale and c at zero. the contents of the dac registers are cleared, setting all analog outputs to 0 v. the soft reset activation time is 135 s max.
ad5382 rev. 0 | page 23 of 40 table 16. control register contents msb lsb cr13 cr12 cr11 cr10 cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 control register write/read reg1 = reg0 = 0, a4Ca0 = 01100, r/ w status determines if the operation is a write (r/ w = 0) or a read (r/ w = 1). db13 to db0 contains the control register data. control register contents cr13: power-down status. this bit is used to configure the output amplifier state in power down. cr13 = 1. amplifier output is high impedance (default on power-up). cr13 = 0. amplifier output is 100 k? to ground. cr12: ref select. this bit selects the operating internal reference for the ad5382. cr12 is programmed as follows: cr12 = 1: internal reference is 2.5 v (ad5382-5 default), the recommended operating reference for ad5382-5. cr12 = 0: internal reference is 1.25 v (ad5382-3 default), the recommended operating reference for ad5382-3. cr11: current boost control. this bit is used to boost the current in the output amplifier, thereby altering its slew rate. this bit is configured as follows: cr11 = 1: boost mode on. this maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation. cr11 = 0: boost mode off (default on power-up). this reduces the bias current in the output amplifier and reduces the overall power consumption. cr10: internal/external reference. this bit determines if the dac uses its internal reference or an externally applied reference. cr10 = 1: internal reference enabled. the reference output depends on data loaded to cr12. cr10 = 0: external reference selected (default on power up). cr9: channel monitor enable (see channel monitor function) cr9 = 1: monitor enabled. this enables the channel monitor function. after a write to the monitor channel in the sfr register, the selected channel output is routed to the mon_out pin. cr9 = 0: monitor disabled (default on power-up). when the monitor is disabled, mon_out is three-stated. cr8: thermal monitor function. this function is used to monitor the ad5382s internal die temperature when enabled. the thermal monitor powers down the output amplifiers when the temperature exceeds 130c. th is function can be used to protect the device in cases where power dissipation may be exceeded if a number of output channels are simultaneously short-circuited. a soft power-up will re-enable the output amplifiers if the die temperature has dropped below 130c. cr8 = 1: thermal monitor enabled. cr8 = 0: thermal monitor disabled (default on power- up). cr7 and cr6: dont care. cr5 to cr2: toggle function enable. this function allows the user to toggle the output between two codes loaded to the a and b register for each dac. control register bits cr5 to cr2 are used to enable individual groups of eight channels for opera- tion in toggle mode. a logic 1 written to any bit enables a group of channels; a logic 0 disables a group. ldac is used to toggle between the two registers. table 17 shows the decoding for toggle mode operation. for example, cr5 controls group 3, which contains channels 24 to 31, cr5 = 1 enables these channels . cr1 and cr0: dont care. table 17. cr bit group channels cr5 3 24C31 cr4 2 16C23 cr3 1 8C15 cr2 0 0C7 channel monitor function reg1 = reg0 = 0, a4Ca0 = 01010 db13Cdb8 = contain data to address the monitored channel. a channel monitor function is provided on the ad5382. this feature, which consists of a multiplexer addressed via the interface, allows any channel output or the signals connected to the mon_in inputs to be routed to the mon_out pin for monitoring using an external adc. the channel monitor function must be enabled in the control register before any channels are routed to mon_out. on the ad5382, db13 to db8 contain the channel address for the monitored channel. selecting channel address 63 three-states mon_out.
ad5382 rev. 0 | page 24 of 40 table 18. ad5382 channel monitor decoding reg1 reg0 a4 a3 a2 a1 a0 db13 db12 db11 db10 db9 db 8 db7Cdb0 mon_out 0 0 0 1 0 1 0 0 0 0 0 0 0 x vout0 0 0 0 1 0 1 0 0 0 0 0 0 1 x vout1 0 0 0 1 0 1 0 0 0 0 0 1 0 x vout2 0 0 0 1 0 1 0 0 0 0 0 1 1 x vout3 0 0 0 1 0 1 0 0 0 0 1 0 0 x vout4 0 0 0 1 0 1 0 0 0 0 1 0 1 x vout5 0 0 0 1 0 1 0 0 0 0 1 1 0 x vout6 0 0 0 1 0 1 0 0 0 0 1 1 1 x vout7 0 0 0 1 0 1 0 0 0 1 0 0 0 x vout8 0 0 0 1 0 1 0 0 0 1 0 0 1 x vout9 0 0 0 1 0 1 0 0 0 1 0 1 0 x vout10 0 0 0 1 0 1 0 0 0 1 0 1 1 x vout11 0 0 0 1 0 1 0 0 0 1 1 0 0 x vout12 0 0 0 1 0 1 0 0 0 1 1 0 1 x vout13 0 0 0 1 0 1 0 0 0 1 1 1 0 x vout14 0 0 0 1 0 1 0 0 0 1 1 1 1 x vout15 0 0 0 1 0 1 0 0 1 0 0 0 0 x vout16 0 0 0 1 0 1 0 0 1 0 0 0 1 x vout17 0 0 0 1 0 1 0 0 1 0 0 1 0 x vout18 0 0 0 1 0 1 0 0 1 0 0 1 1 x vout19 0 0 0 1 0 1 0 0 1 0 1 0 0 x vout20 0 0 0 1 0 1 0 0 1 0 1 0 1 x vout21 0 0 0 1 0 1 0 0 1 0 1 1 0 x vout22 0 0 0 1 0 1 0 0 1 0 1 1 1 x vout23 0 0 0 1 0 1 0 0 1 1 0 0 0 x vout24 0 0 0 1 0 1 0 0 1 1 0 0 1 x vout25 0 0 0 1 0 1 0 0 1 1 0 1 0 x vout26 0 0 0 1 0 1 0 0 1 1 0 1 1 x vout27 0 0 0 1 0 1 0 0 1 1 1 0 0 x vout28 0 0 0 1 0 1 0 0 1 1 1 0 1 x vout29 0 0 0 1 0 1 0 0 1 1 1 1 0 x vout30 0 0 0 1 0 1 0 0 1 1 1 1 1 x vout31 0 0 0 1 0 1 0 1 0 0 0 0 0 x mon_in1 0 0 0 1 0 1 0 1 0 0 0 0 1 x mon_in2 0 0 0 1 0 1 0 1 0 0 1 0 x mon_in3 0 0 0 1 0 0 1 0 0 0 1 1 x mon_in4 0 0 0 1 0 1 0 1 0 0 1 0 0 x undefined 0 0 0 1 0 1 0 1 0 0 1 0 1 x undefined ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 1 0 1 0 1 1 1 1 1 0 x undefined 0 0 0 1 0 1 0 1 1 1 1 1 1 x three-state 03733-0-003 db13?db8 channel address ad5382 channel monitor decoding 0001010 vout0 vout1 vout31 vout30 mon_out reg1 reg0 a4 a3 a2 a1 a0 mon_in1 mon_in2 mon_in3 mon_in4 figure 28. channel monitor decoding
ad5382 rev. 0 | page 25 of 40 hardware functions reset function bringing the reset line low resets the contents of all internal registers to their power-on reset state. reset is a negative edge- sensitive input. the default corresponds to m at full scale and to c at zero. the contents of the dac registers are cleared, setting vout 0 to vout 31 to 0 v. this sequence takes 270 s max. the falling edge of reset initiates the reset process; busy goes low for the duration, returning high when reset is complete. while busy is low, all interfaces are disabled and all ldac pulses are ignored. when busy returns high, the part resumes normal operation and the status of the reset pin is ignored until the next falling edge is detected. asynchronous clear function bringing the clr line low clears the contents of the dac registers to the data contained in the user configurable clr register and sets vout 0 to vout 31 accordingly. this func- tion can be used in system calibration to load zero scale and full scale to all channels. the execution time for a clr is 35 s. busy and ldac functions busy is a digital cmos output that indicates the status of the ad5382. the value of x2, the internal data loaded to the dac data register, is calculated each time the user writes new data to the corresponding x1, c, or m registers. during the calculation of x2, the busy output goes low. while busy is low, the user can continue writing new data to the x1, m, or c registers, but no dac output updates can take place. the dac outputs are updated by taking the ldac input low. if ldac goes low while busy is active, the ldac event is stored and the dac outputs update immediately after busy goes high. the user may hold the ldac input permanently low, in which case the dac outputs update immediately after busy goes high. busy also goes low during power-on reset and when a falling edge is detected on the reset pin. during this time, all interfaces are disabled and any events on ldac are ignored. the ad5382 contains an extra feature whereby a dac register is not updated unless its x2 register has been written to since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the x2 registers. however, the ad5382 will only update the dac register if the x2 data has changed, thereby removing unnecessary digital crosstalk. fifo operation in parallel mode the ad5382 contains a fifo to optimize operation when operating in parallel interface mode. the fifo enable (level sensitive, active high) is used to enable the internal fifo. when connected to dvdd, the internal fifo is enabled, allowing the user to write to the device at full speed. fifo is only available in parallel interface mode. the status of the fifo_en pin is sampled on power-up, and after a clear or reset, to determine if the fifo is enabled. in either serial or i 2 c interface modes, fifo_en should be tied low. up to 128 successive instructions can be written to the fifo at maximum speed in parallel mode. when the fifo is full, any further writes to the device are ignored. figure 29 shows a comparison between fifo mode and non-fifo mode in terms of channel update time. figure 29 also outlines digital loading time. number of writes time ( s) 1 4 7 10 13 16 19 22 25 28 31 34 37 0 10 5 15 25 20 40 without fifo (channel update time) with fifo (channel update time) with fifo (digital loading time) 03731-0-018 figure 29. channel update rate (fifo vs. non-fifo) power-on reset the ad5382 contains a power-on reset generator and state machine. the power-on reset resets all registers to a predefined state and configures the analog outputs as high impedance. the busy pin goes low during the power-on reset sequencing, preventing data writes to the device. power-down the ad5382 contains a global power-down feature that puts all channels into a low power mode and reduces the analog power consumption to 2 a max and digital power consumption to 20 a max. in power-down mode, the output amplifier can be configured as a high impedance output or provide a 100 k? load to ground. the contents of all internal registers are retained in power-down mode. when exiting power-down, the settling time of the amplifier will elapse before the outputs settle to their correct values.
ad5382 rev. 0 | page 26 of 40 ad5382 interfaces the ad5382 contains both parallel and serial interfaces. furthermore, the serial interface can be programmed to be either spi, dsp, microwire, or i 2 c compatible. the ser/ par pin selects parallel and serial interface modes. in serial mode, the spi /i2c pin is used to select dsp, spi, microwire, or i 2 c interface mode. the devices use an internal fifo memory to allow high speed successive writes in parallel interface mode. the user can con- tinue writing new data to the device while write instructions are being executed. the busy signal indicates the current status of the device, going low while instructions in the fifo are being executed. in parallel mode, up to 128 successive instructions can be written to the fifo at maximum speed. when the fifo is full, any further writes to the device are ignored. to minimize both the power consumption of the device and the on-chip digital noise, the active interface only powers up fully when the device is being written to, i.e., on the falling edge of wr or the falling edge of sync . dsp, spi, microwire compatible serial interfaces the serial interface can be operated with a minimum of three wires in standalone mode or four wires in daisy-chain mode. daisy chaining allows many devices to be cascaded together to increase system channel count. the ser/ par pin must be tied high and the spi /i2c pin (pin 97) should be tied low to enable the dsp/spi/microwire compatible serial interface. in serial interface mode, the user does not need to drive the parallel input data pins. the serial interfaces control pins are sync , din, sclk standard 3-wire interface pins. dcen selects standalone mode or daisy-chain mode. sdo data out pin for daisy-chain mode. figure 3 and figure 5 show timing diagrams for a serial write to the ad5382 in standalone and daisy-chain modes. the 24-bit data-word format for the serial interface is shown in table 19 a /b . when toggle mode is enabled, this pin selects whether the data write is to the a or b register. with toggle disabled, this bit should be set to zero to select the a data register. r/ w is the read or write control bit. a4Ca0 are used to address the input channels. reg1 and reg0 select the register to which data is written, as shown in table 11. db13Cdb0 contain the input data-word. x is a dont care condition. standalone mode by connecting the dcen (daisy-chain enable) pin low, stand- alone mode is enabled. the serial interface works with both a continuous and a noncontinuous serial clock. the first falling edge of sync starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. any further edges on sync except for a falling edge are ignored until 24 bits are clocked in. once 24 bits have been shifted in, the sclk is ignored. in order for another serial transfer to take place, the counter must be reset by the falling edge of sync . table 19. 32-channel, 14-bit dac serial input register configuration msb lsb a /b r/ w 0 a4 a3 a2 a1 a0 reg1 reg0 db13 db12 db11 db10 db9 db8 db7 db6 db 5 db4 db3 db2 db1 db0
ad5382 rev. 0 | page 27 of 40 daisy-chain mode for systems that contain several devices, the sdo pin may be used to daisy-chain several devices together. this daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. by connecting the dcen (daisy-chain enable) pin high, daisy- chain mode is enabled. the first falling edge of sync starts the write cycle. the sclk is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting the sdo of the first device to the din input on the next device in the chain, a multidevice interface is constructed. twenty-four clock pulses are required for each device in the system. therefore, the total number of clock cycles must equal 24n, where n is the total number of ad538x devices in the chain. when the serial transfer to all devices is complete, sync is taken high. this latches the input data in each device in the daisy-chain and prevents any further data from being clocked into the input shift register. if the sync is taken high before 24 clocks are clocked into the part, this is considered a bad frame and the data is discarded. the serial clock may be either a continuous or a gated clock. a continuous sclk source can only be used if it can be arranged that sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used and sync must be taken high after the final clock to latch the data. readback mode readback mode is invoked by setting the r/ w bit = 1 in the serial input register write. with r/ w = 1, bits a4 to a0, in association with bits reg1 and reg0, select the register to be read. the remaining data bits in the write sequence are dont cares. during the next spi write, the data appearing on the sdo output will contain the data from the previously addressed register. for a read of a single register, the nop command can be used in clocking out the data from the selected register on sdo. figure 30 shows the readback sequence. for example, to read back the m register of channel 0 on the ad5382, the following sequence should be implemented. first, write 0x404xxx to the ad5382 input register. this configures the ad5382 for read mode with the m register of channel 0 selected. note that data bits db13 to db0 are dont cares. follow this with a second write, a nop condition, 0x000000. during this write, the data from the m register is clocked out on the dout line, i.e., data clocked out will contain the data from the m register in bits db13 to db0, and the top 10 bits contain the address information as previously written. in readback mode, the sync signal must frame the data. data is clocked out on the rising edge of sclk and is valid on the falling edge of the sclk signal. if the sclk idles high between the write and read operations of a readback operation, the first bit of data is clocked out on the falling edge of sync . 03731-0-019 24 48 sclk sync din sdo undefined selected register data clocked out nop condition input word specifies register to be read db23 db0 db0 db23 db23 db0 db0 db23 figure 30. serial readback operation
ad5382 rev. 0 | page 28 of 40 i 2 c serial interface the ad5382 features an i 2 c compatible 2-wire interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate communication between the ad5382 and the master at rates up to 400 khz. figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation. in selecting the i 2 c operating mode, first configure serial operating mode (ser/ par = 1) and then select i 2 c mode by configuring the spi /i2c pin to a logic 1. the device is connected to the i 2 c bus as a slave device (i.e., no clock is generated by the ad5382). the ad5382 has a 7-bit slave address 1010 1ad1ad0. the 5 msb are hard-coded and the 2 lsb are determined by the state of the ad1 and ad0 pins. the facility to hardware configure ad1 and ad0 allows four of these devices to be configured on the bus. i 2 c data transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are control signals that configure start and stop conditions. both sda and scl are pulled high by the external pull-up resistors when the i 2 c bus is not busy. start and stop conditions a master device initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with scl high. a stop condition is a low-to-high transition on sda while scl is high. a start condition from the master signals the beginning of a transmission to the ad5382. the stop condition frees the bus. if a repeated start condition (sr) is generated instead of a stop condition, the bus remains active. repeated start conditions a repeated start (sr) condition may indicate a change of data direction on the bus. sr may be used when the bus master is writing to several i 2 c devices and wants to maintain control of the bus. acknowledge bit (ack) the acknowledge bit (ack) is the ninth bit attached to any 8-bit data-word. ack is always generated by the receiving device. the ad5382 devices generate an ack when receiving an address or data by pulling sda low during the ninth clock period. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication. ad5382 slave addresses a bus master initiates communication with a slave device by issuing a start condition followed by the 7-bit slave address. when idle, the ad5382 waits for a start condition followed by its slave address. the lsb of the address word is the read/ wr ite (r/ w ) bit. the ad5382 is a receive only device; when communicating with the ad5382, r/ w = 0. after receiving the proper address 1010 1ad1ad0 , the ad5382 issues an ack by pulling sda low for one clock cycle. the ad5382 has four different user programmable addresses determined by the ad1 and ad0 bits. write operation there are three specific modes in which data can be written to the ad5382 dac. 4-byte mode when writing to the ad5382 dacs, the user must begin with an address byte (r/ w = 0) after which the dac will acknowl- edge that it is prepared to receive data by pulling sda low. the address byte is followed by the pointer byte; this addresses the specific channel in the dac to be addressed and is also acknowledged by the dac. two bytes of data are then written to the dac, as shown in figure 31. a stop condition follows. this allows the user to update a single channel within the ad5382 at any time and requires four bytes of data to be transferred from the master. 3-byte mode in 3-byte mode, the user can update more than one channel in a write sequence without having to write the device address byte each time. the device address byte is only required once; sub- sequent channel updates require the pointer byte and the data bytes. in 3-byte mode, the user begins with an address byte (r/ w = 0), after which the dac will acknowledge that it is prepared to receive data by pulling sda low. the address byte is followed by the pointer byte. this addresses the specific channel in the dac to be addressed and is also acknowledged by the dac. this is then followed by the two data bytes. reg1 and reg0 determine the register to be updated. if a stop condition does not follow the data bytes, another channel can be updated by sending a new pointer byte followed by the data bytes. this mode only requires three bytes to be sent to update any channel once the device has been initially addressed, and reduces the software overhead in updating the ad5382 channels. a stop condition at any time exits this mode. figure 32 shows a typical configuration.
ad5382 rev. 0 | page 29 of 40 1 0 1 0 1 ad1 ad0 r/w 0 0 0 a4 a3 a2 a1 a0 scl sd a scl sd a start cond by master ack by ad538x ack by ad538x address byte most significant byte least significant byte pointer byte msb ack by ad538x ack by ad538x stop cond by master reg1 reg0 msb lsb msb lsb 03731-0-020 figure 31. 4-byte ad5382, i 2 c write operation 03731-0-021 scl s d a s d a scl s d a scl s d a scl start cond by master ack by ad538x msb address byte pointer byte for channel "n" most significant data byte pointer byte for channel "next channel" least significant data byte most significant data byte least significant data byte ack by ad538x ack by ad538x data for channel "n" data for channel "next channel" ack by ad538x 1 0 0 0 a4a3a2a1a0 0 1 0 0 0 0 a4a3a2a1a0 1 ad1 ad0 r/w reg1 reg0 msb lsb msb lsb msb ack by ad538x ack by ad538x ack by ad538x stop cond by master reg1 reg0 msb lsb msb lsb figure 32. 3-byte ad5382, i 2 c write operation
ad5382 rev. 0 | page 30 of 40 2-byte mode following initialization of 2-byte mode, the user can update channels sequentially. the device address byte is only required once and the pointer address pointer is configured for auto- increment or burst mode. the user must begin with an address byte (r/ w = 0), after which the dac will acknowledge that it is prepared to receive data by pulling sda low. the address byte is followed by a specific pointer byte (0xff) that initiates the burst mode of operation. the address pointer initializes to channel zero, the data following the pointer is loaded to channel 0, and the address pointer automatically increments to the next address. the reg0 and reg1 bits in the data byte determine which register will be updated. in this mode, following the initializa- tion, only the two data bytes are required to update a channel. the channel address automatically increments from address 0 to channel 31 and then returns to the normal 3-byte mode of operation. this mode allows transmission of data to all channels in one block and reduces the software overhead in configuring all channels. a stop condition at any time exits this mode. toggle mode is not supported in 2-byte mode. figure 33 shows a typical configuration. parallel interface the ser/ par pin must be tied low to enable the parallel interface and disable the serial interfaces. figure 7 shows the timing diagram for a parallel write. the parallel interface is controlled by the following pins: cs pin active low device select pin. wr pin on the rising edge of wr , with cs low, the addresses on pins a4 to a0 are latched; data present on the data bus is loaded into the selected input registers. reg0, reg1 pins the reg0 and reg1 pins determine the destination register of the data being written to the ad5382. see table 11. pins a4 to a0 each of the 40 dac channels can be addressed individually. pins db13 to db0 the ad5382 accepts a straight 14-bit parallel word on db13 to db0, where db13 is the msb and db0 is the lsb. 1 0 1 0 1 ad1 ad0 r/w a7 = 1 a6 = 1 a5 = 1 a4 = 1 a3 = 1 a2 = 1 a1 = 1 a0 = 1 start cond by master address byte pointer byte most significant data byte channel 0 data least significant data byte ack by converter msb ack by converter ack by ad538x ack by ad538x most significant data byte channel 1 data least significant data byte ack by converter ack by converter most significant data byte channel n data followed by stop least significant data byte ack by converter ack by converter stop cond by master reg1 reg0 msb lsb msb lsb reg1 reg0 msb lsb msb lsb reg1 reg0 msb lsb msb lsb scl sda scl sda scl sda scl sda 03731-0-022 figure 33. 2-byte, i 2 c write operation
ad5382 rev. 0 | page 31 of 40 microprocessor interfacing parallel interface the ad5382 can be interfaced to a variety of 16-bit microcon- trollers or dsp processors. figure 35 shows the ad5382 family interfaced to a generic 16-bit microcontroller/dsp processor. the lower address lines from the processor are connected to a0Ca4 on the ad5382. the upper address lines are decoded to provide a cs , ldac s ignal for the ad5382. the fast interface timing of the ad5382 allows direct interface to a wide variety of microcontrollers and dsps, as shown in figure 35. ad5382 to mc68hc11 the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock polarity bit (cpol) = 0, and the clock phase bit (cpha) = 1. the spi is configured by writing to the spi control register (spcr)see the 68hc11 user manual. sck of the 68hc11 drives the sclk of the ad5382, the mosi output drives the serial data line (d in ) of the ad5382, and the miso input is driven from d out . the sync signal is derived from a port line (pc7). when data is being transmitted to the ad5382, the sync line is taken low (pc7). data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. 03733-0-004 mc68hc11 ad5382 miso mosi sck pc7 sdo reset ser/par din sclk sync spi/i2c dv dd figure 34. ad5382-to-mc68hc11 interface 03733-0-005 controller/ dsp processor* ad5382 address decode upper bits of address bus data bus d15 d0 a4 a3 a2 a1 a0 r/w a4 a3 a2 a1 a0 wr reg1 reg0 d13 d0 cs ldac *additional pins omitted for clarity figure 35. ad5382-to-parallel interface
ad5382 rev. 0 | page 32 of 40 ad5382 to pic16c6x/7x the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit = 0. this is done by writing to the synchronous serial port control register (sspcon). see the pic16/17 microcontroller user manual. in this example i/o, port ra1 is being used to pulse sync and enable the serial port of the ad5382. this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write operations may be needed depending on the mode. figure 36 shows the connection diagram. 03733-0-006 pic16c6x/7x ad5382 sdi/rc4 sdo/rc5 sck/rc3 ra1 sdo reset ser/par din sclk sync spi/i2c dv dd figure 36. ad5382-to-pic16c6x/7x interface ad5382 to 8051 the ad5382 requires a clock synchronized to the serial data. the 8051 serial interface must therefore be operated in mode 0. in this mode, serial data enters and exits through rxd, and a shift clock is output on txd. figure 37 shows how the 8051 is connected to the ad5382. because the ad5382 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. the ad5382 requires its data to be msb first. since the 8051 outputs the lsb first, the transmit routine must take this into account. 03733-0-007 8xc51 ad5382 rxd txd p1.1 sdo reset ser/par din sclk sync spi/i2c dv dd figure 37. ad5382-to-8051 interface ad5382 to adsp-2101/adsp-2103 figure 38 shows a serial interface between the ad5382 and the adsp-2101/adsp-2103. the adsp-2101/adsp-2103 should be set up to operate in sport transmit alternate framing mode. the adsp-2101/adsp-2103 sport is programmed through the sport control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. 03733-0-008 adsp-2101/ adsp-2103 ad5382 dr dt sck tfs rfs sdo reset ser/par din sclk dv dd spi/i2c sync figure 38. ad5382-to-adsp -2101/adsp-2103 interface
ad5382 rev. 0 | page 33 of 40 application information power supply decoupling in any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5382 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5382 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only, a star ground point established as close to the device as possible. for supplies with multiple pins (av dd , dv dd ), these pins should be tied together. the ad5382 should have ample supply bypass- ing of 10 f in parallel with 0.1 f on each supply, located as close to the package as possible and ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. the power supply lines of the ad5382 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. a ground line routed between the d in and sclk lines will help reduce crosstalk between them (this is not required on a multilayer board because there will be a separate ground plane, but separating the lines will help). it is essential to minimize noise on the v in and refin lines. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a micro- strip technique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side. typical configuration circuit figure 39 shows a typical configuration for the ad5382-5 when configured for use with an external reference. in the circuit shown, all agnd, signal_gnd, and dac_gnd pins are tied together to a common agnd. agnd and dgnd are connected together at the ad5382 device. on power-up, the ad5382 defaults to external reference operation. all av dd lines are connected together and driven from the same 5 v source. it is recommended to decouple close to the device with a 0.1 f ceramic and a 10 f tantalum capacitor. in this application, the reference for the ad5382-5 is provided externally from either an adr421 or adr431 2.5 v reference. suitable external references for the ad5382-3 include the adr280 1.2 v reference. the reference should be decoupled at the refout/refin pin of the device with a 0.1 f capacitor. 03733-0-009 adr431/ adr421 ad5382-5 avdd dvdd signal gnd dac gnd dgnd vout31 vout0 agnd refout/refin refgnd 0.1 f 10 f 0.1 f 0.1 f avdd dvdd figure 39. typical configuration with external reference figure 40 shows a typical configuration when using the internal reference. on power-up, the ad5382 defaults to an external reference; therefore, the internal reference needs to be configured and turned on via a write to the ad5382 control register. control register bit cr12 allows the user choose the reference value; bit cr 10 is used to select the internal reference. it is recommended to use the 2.5 v reference when av dd = 5 v, and the 1.25 v reference when av dd = 3 v. 03733-0-010 ad5382 avdd dvdd signal gnd dac gnd dgnd vout31 vout0 agnd refout/refin refgnd 0 .1 f 10 f 0.1 f 0.1 f avdd dvdd figure 40. typical configuration with internal reference digital connections have been omitted for clarity. the ad5382 contains an internal power- on reset circuit with a 10 ms brownout time. if the power supply ramp rate exceeds 10 ms, the user should reset the ad5382 as part of the initialization process to ensure the calibration data gets loaded correctly into the device.
ad5382 rev. 0 | page 34 of 40 ad5382 monitor function the ad5382 contains a channel monitor function that consists of a multiplexer addressed via the interface, allowing any chan- nel output to be routed to this pin for monitoring using an external adc. the channel monitor function must be enabled in the control register before any channels are routed to mon_out. table 18 contains the decoding information required to route any channel to mon_out. external signals within the ad5382s absolute max input range can be connected to the mon_in pins and monitored at mon_out. selecting channel address 63 three-states mon_out. figure 41 shows a typical monitoring circuit implemented using a 12-bit sar adc in a 6-lead sot-23 package. the controller output port selects the channel to be monitored, and the input port reads the converted data from the adc. toggle mode function the toggle mode function allows an output signal to be gener- ated using the ldac control signal that switches between two dac data registers. this function is configured using the sfr control register as follows. a write with reg1 = reg0 = 0 and a4Ca0 = 01100 specifies a control register write. the toggle mode function is enabled in groups of eight channels using bits cr5 to cr2 in the control register. see the ad5382 control register description. figure 42 shows a block diagram of toggle mode implementation. each of the 32 dac channels on the ad5382 contain an a and b data register. note that the b registers can only be loaded when toggle mode is enabled. the sequence of events when configuring the ad5382 for toggle mode is 1. enable toggle mode for the required channels via the control register. 2. load data to a registers. 3. load data to b registers. 4. apply ldac . the ldac is used to switch between the a and b registers in determining the analog output. the first ldac configures the output to reflect the data in the a registers. this mode offers significant advantages if the user wants to generate a square wave at the output of all 32 channels, as might be required to drive a liquid crystal based variable optical attenuator. in this case, the user writes to the control register and enables the toggle function by setting cr5 to cr2 = 1, thus enabling the four groups of eight for toggle mode operation. the user must then load data to all 32 a and b registers. toggling ldac will set the output values to reflect the data in the a and b registers. the frequency of the ldac determines the frequency of the square wave output. toggle mode is disabled via the control register. the first ldac following the disabling of the toggle mode will update the outputs with the data contained in the a registers. ad7476 gnd sdata cs sclk avcc v in mon_out agnd din sync sclk dac_gnd signal_gnd vout0 vout31 avcc ad5382 output port input port controller 03733-0-011 a d 7 8 0 / a d r 4 3 1 refout/refin mon_in1 mon_in2 avcc figure 41. typical channel monitoring circuit
ad5382 rev. 0 | page 35 of 40 14-bit dac dac register input data input register data register b data register a a/b v out ldac control input 03731-0-029 figure 42. toggle mode function actuators for mems mirror array sensor and multiplexer 8-channel adc (ad7856) or single channel adc (ad7671) ad5382 14-bit dac 14-bit dac ref out ref in avdd vo1 vo31 g = 50 g = 50 output range 0?200v adsp-21065l 0.01 f 03733-0-012 +5v figure 43. ad5382 in a mems based optical switch thermal monitor function the ad5382 contains a temperature shutdown function to protect the chip in case multiple outputs are shorted. the short circuit current of each output amplifier is typically 40 ma. operating the ad5382 at 5 v leads to a power dissipation of 200 mw per shorted amplifier. with five channels shorted, this leads to an extra watt of power dissipation. for the 100-lead lqfp, the ja is typically 44c/w. the thermal monitor is enabled by the user via cr8 in the control register. the output amplifiers on the ad5382 are automatically powered down if the die temperature exceeds approximately 130c. after a thermal shutdown has occurred, the user can re-enable the part by executing a soft power-up if the temperature has dropped below 130c or by turning off the thermal monitor function via the control register. ad5382 in a mems based optical switch in their feed-forward control paths, mems based optical switches require high resolution dacs that offer high channel density with 14-bit monotonic behavior. the 32-channel, 14-bit ad5382 dac satisfies these requirements. in the circuit in figure 43, the 0 v to 5 v outputs of the ad5382 are amplified to achieve an output range of 0 v to 200 v, which is used to control actuators that determine the position of mems mirrors in an optical switch. the exact position of each mirror is measured using sensors. the sensor outputs are multiplexed into a high resolution adc in determining the mirror position. the control loop is closed and driven by an adsp-21065l, a 32-bit sharc? dsp with an spi compatible sport interface. the adsp- 21065l writes data to the dac, controls the multiplexer, and reads data from the adc via the serial interface.
ad5382 rev. 0 | page 36 of 40 optical attenuators based on its high channel count, high resolution, monotonic behavior, and high level of integration, the ad5382 is ideally targeted at optical attenuation applications used in dynamic gain equalizers, variable optical attenuators (voa), and optical add-drop multiplexers (oadm). in these applications, each wavelength is individually extracted using an arrayed wave guide; its power is monitored using a photodiode, transimped- ance amplifier and adc in a closed-loop control system. the ad5382 controls the optical attenuator for each wavelength, ensuring that the power is equalized in all wavelengths before being multiplexed onto the fiber. this prevents information loss and saturation from occurring at amplification stages further along the fiber. attenuator attenuator attenuator attenuator awg awg fibre fibre dwdm out optical switch 11 12 1n?1 1n dwdm in ad5382, 32-channel, 14-bit dac n:1 multiplexer 16-bit adc controller tia/log amp (ad8304/ad8305) adg731 (32:1 mux) ad7671 (0-5v, 1msps) photodiodes add ports drop ports 03733-0-013 figure 44. oadm using the ad5382 as part of an optical attenuator
ad5382 rev. 0 | page 37 of 40 outline dimensions top view (pins down) 1 25 26 51 50 75 76 100 14.00 bsc sq 0.50 bsc 0.27 0.22 0.17 1.60 max seating plane 12 typ 0.75 0.60 0.45 view a 16.00 bsc sq 12.00 ref 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 pin 1 compliant to jedec standards ms-026bed figure 45. 100-lead leaded quad flatpack [lqfp] (st-100) dimensions shown in millimeters ordering guide model resolution temperature range av dd range output channels linearity error package description package option ad5382bst-3 14 bits C40c to +85c 2.7 v to 3.6 v 40 4 lsb 100-lead lqfp st-100 AD5382BST-3-REEL 14 bits C40c to +85c 2.7 v to 3.6 v 40 4 lsb 100-lead lqfp st-100 ad5382bst-5 14 bits C40c to +85c 4.5 v to 5.5 v 40 4 lsb 100-lead lqfp st-100 ad5382bst-5-reel 14 bits C40c to +85c 4.5 v to 5.5 v 40 4 lsb 100-lead lqfp st-100 eval-ad5382eb evaluation kit
ad5382 rev. 0 | page 38 of 40 notes
ad5382 rev. 0 | page 39 of 40 notes
ad5382 rev. 0 | page 40 of 40 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03733C0C5/04(0)

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